Inline HDL - 2024.2 English - UG994

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2024-11-13
Version
2024.2 English

IP integrator offers you a variety of useful utility IPs that you can use to create your own designs. You can use both packaged and utility IP's as HDL constructs in IP integrator. Using HDL constructs exponentially reduces the processing requirements for IPs enhancing performance for larger designs that use these IPs. In the IP catalog, along with utility IPs, new inline HDL are also available for use. You can add an inline HDL to your design by searching for it in the IP catalog like for other IPs. Inline IP names start with the keyword inline and can be found under the Inline HDL section in Vivado IP catalog as shown in the following image.

The current Vivado release supports the following inline HDL IPs:

  • Inline Concat
  • Inline Constant
  • Inline Slice
  • Inline Utility Reduced Logic
  • Inline Utility Vector Logic

Using inline HDL IPs offers the following benefits:

  1. Reduces number of files on disk and file I/O operations
  2. Reduces overall runtime of the following commands:
    • open_bd_design
    • save_bd_design
    • generate_target
  3. Reduces number of OOC runs and associated runs management overhead
  4. Reduces netlist elaboration time because of the reduced number of modules
  5. Reduces project archive size
  6. Supports VHDL target language
  7. Supports project part change
  8. Supports read_bd flow and packaged BD Flow
  9. Supports platform flow for ilconcat blocks that are equivalent to xlconcat blocks