Implementing the Design - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English
Next the design can be implemented and a bitstream generated for the design.
  1. In the Flow Navigator, under Program and Debug, click Run Implementation or Generate Bitstream.

    You are prompted as needed by the Vivado tool to save constraints, and launch implementation.

  2. In the Bitstream Generation Completed dialog box, click Open Implemented Design.

  3. Verify timing by looking at the Timing Summary report.
  4. Ensure that block RAM INIT strings are populated with the ELF data.
    1. From the main menu, select Edit > Find, as shown in the following figure.

    2. In the Find window, set the PRIMITIVE_TYPE to BMEM.BRAM.
    3. Click OK.
    4. In the Find Results window, select an instance of the block RAM and verify that the INIT properties have been populated in the Cell Properties window, shown in the following figure.