IP to GT Integration - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

To enable GT sharing, AMD IP that uses GT components does not integrate the GT components in the IP. Instead, the AMD IP is added standalone in the Vivado IP integrator, and block automation is used to connect TX and RX data paths of the IP to the GT Wizard. A new GT Wizard Quad base is launched if it cannot pack the parent IP with existing GT Quad resources. It also uses optional usrclk, outclk, REFCLK, and reset connections. For an overview of creating a design with GT parent IP, see Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331). For information on the block automation options, see the respective AMD IP product guides.