Single BD Design
This feature can be used if user decided that they wish to lock 'N' address segments at their current addresses while moving the remainder of the segments to new addresses.
- You can lock the Block RAM using the Tcl command
set_property locktype local [get_bd_addr_segs {versal_cips_0/FPD_CCI_NOC_0/SEG_axi_bram_ctrl_0_Mem0}]. Following is theCIPS_DDR_PL_debugexample design, which locks the block RAM at their current addresses but assigns everything else.You can also lock the block RAM using the GUI as shown in the following figure.
- After the segment is locked, it is grayed out in the address editor as shown
in the following image.
-
Unassign all would
unassign every master segment in the design, except for the segments locked,
that is, CIPS- block RAM address segment.
- Locked segments cannot be unassigned individually, nor can their ranges or offsets be changed, while they are in the locked state.
- You then can call assign BD address to reassign all except the locked
segment.
Multiple BD Design
Addressing can be spread out across multiple independent block diagrams that are later combined together into a top design using block containers technology. Locking lets you to define sections of the addressing of individual designs that are fixed and remains so when the design's addressing is combined on top, while leaving the other unlocked parts dynamic.
- Following is an example use case that describes how this feature is useful
to you with block containers. Consider the CIPS_DDR_PL_debug example design with
block RAM inside block container is mapped to CIPS through NOC.
- The source diagram for the block container BRAMs and the address editor
looks as follows.
- Locking globally the address segment in source BD, it would remain locked in
top BD as well.
Note: If the source BD (that is, in BRAMs.bd) address segment is locked local instead of global, the address segment would remain unlocked in top BD (that is, cips_dd_pl_debug.bd).