Cross-Probing Timing Paths - 2024.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2024-05-30
Version
2024.1 English
Many times you need to probe a timing issue after implementation to a source block in IP Integrator design. This can be useful when you are not intimately aware of a design inherited from another team member. To isolate a timing path to a particular block, click the link to point to the source block of the timing issue in question on the block design canvas to open the implemented design. An example of a warning on an IP block in an implemented design is shown in the following figure.
Figure 1. Methodology Warning
The following message is displayed:
CLKC #1 The MMCME3 cell config_mb_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/mmcme3_adv_inst has COMPENSATION value ZHOLD, but CLKOUT2 output drives sequential IO cells. In order to achieve insertion delay and phase-alignment for the IO sequential cells, CLKOUT0 must be used. 

As you can see in the message, the path cell config_mb_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/mmcme3_adv_inst has a link. Clicking this link will take you to the block design canvas and highlight the block design cell related to this timing message.

To see the cell in question on the block design canvas, click IP INTEGRATOR in Flow Navigator to switch view to the Block Design Canvas.
Figure 2. Highlighted Cell in the Message on the Block Design Canvas

Once the offending cell or IP block has been identified, you can look at the source code or the constraints file to identify the issue.