Creating a Design with Soft Memory Controller IP - 2024.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2024-05-30
Version
2024.1 English

The soft memory controller cores provide solutions for interfacing with the DDR4 SDRAM, RLDRAM3, or QDR IV memory types. Both a complete memory controller and a physical (PHY) layer only solution are supported. The Versal Adaptive SoC soft memory IP for the DDR4 SDRAM, RLDRAM3, and QDR IV cores include the controller, physical layer, and application interface high-level blocks.

You can customize this IP for use in your design by specifying values for the various parameters associated with the IP cores using the following steps:

  1. In the IP catalog, select the IP.
  2. Double-click the selected IP, or select the Customize IP command from the toolbar or right-click menu.
  3. Run connection automation and/or make proper connections. The connection automation feature in the IP integrator helps to connect AXI interfaces along with other automated connections.
  4. Validate the BD design.