Creating a Design with IP for PCIe Subsystems - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The Versal architecture uses two different types of integrated blocks to enable PCIe interface designs. Versal devices can contain one or more instances of a PL-integrated block for PCIe interface designs. Versal devices can also contain one CPM, which resides adjacent to the PS. Multiple versions of both these integrated blocks exist in the Versal architecture. You can configure the Versal adaptive SoC integrated block for PCI Express® interfaces can by double-clicking the selected IP within the IP catalog. The CPM configuration must be configured within the CIPS IP block. For more information, see the following documents:

  • Versal Adaptive SoC CPM CCIX Architecture Manual (AM016)
  • Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
  • Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
  • Versal Adaptive SoC PCIe PHY LogiCORE IP Product Guide (PG345)
  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)