It is permitted to connect ports or pins with different widths in IP integrator.
As seen in the following figure, the bram_addr_a pin of the AXI block RAM controller that is 14-bits wide is
connected to the addra pin of the Block Memory
Generator that is 32-bits wide. The port width mismatch is not flagged during design
validation; however, a warning is issued during the generation of the block design
output products, as follows:
[BD 41-235] Width mismatch when connecting pin: '/axi_bram_ctrl_0_bram/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(14) - Only lower order bits are connected.
The warning indicates that the tool has detected a port width mismatch while connecting the ports or pins, and that only the lower-order bits (the first 14 bits) are connected.
You need to evaluate the warning and take appropriate action as needed. Typically, it is okay to ignore this warning message.