Common Internal Bus Interfaces - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

Some common examples of bus interfaces are buses that conform to the AXI specification such as AXI4, AXI4-Lite, andAXI4-Stream. The AXIMM interface includes all three subsets (AXI4, AXI3, andAXI4-Lite). Other interfaces include block RAM.

I/O Bus Interfaces

Some bus interfaces that group a set of signals going to I/O ports are called I/O interfaces. Examples include: UART, I2C, SPI, Ethernet, PCI® , and DDR.

Special Signals

Special signals include:

  • Clock
  • Reset
  • Interrupt
  • Clock Enable
  • Data for traditional arithmetic IP which do not have any AXI interface, for example adders, subtractors, and multipliers

These special signals are described in the following sections.

Clock

The clock interface can have the following parameters associated with them. These parameters are used in the design generation process and are necessary when the IP is used with other IP in the design.

  • ASSOCIATED_BUSIF: The list contains the names of all bus interfaces that run at this clock frequency. This parameter takes a colon-separated list (:) of strings as its value.

    If there are no interface signals at the boundary that run at this clock rate, leave this field blank.

    Figure 1. ASSOCIATED_BUSIF