BDC Limitations - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English
  • If you add a BDC interface which breaks AXI interconnect cascading, it could cause parameter propagation errors during validation.
  • Prior to creating the BDC, first instantiate an AXI clock converter infrastructure IP (AXI register slice, AXI Data Width converter, AXI clock converter, etc.) between the two cascaded interconnects (outside of the hierarchy). Alternatively, configure the interconnects to have an internal register slice on the side facing the BDC boundary.
  • Once your BDC is locked, do not change the boundary of any source BD to avoid downstream tool errors.
  • Hardened connections, which connect CIPS and the AXI NoC (or AI Engine and NoC) should be at the same hierarchy. The BDC boundary cannot cut across that combination.

    Global mode for synthesis is not supported for a design having BDCs. The tool will automatically default to OOC-per-BD mode when using Global mode in a design having one or more BDC(s). OOC-per-IP is fully supported.