Figure 1. srll
Description
Shifts logically the contents of register rAL, one bit to the right, and places the result in rDL. A zero is shifted in the shift chain and placed in the most significant bit of rDL. The least significant bit coming out of the shift chain is placed in the Carry flag.
Pseudocode
rDL)[0] ← 0
(rDL)[1:63] ← (rAL)[0:62]
MSR[C] ← (rAL)[63]Registers Altered
- rDL
- MSR[C]
Latency
- 1 cycle