Figure 1. srla
Description
Shifts arithmetically the contents of register rAL, one bit to the right, and places the result in rDL. The most significant bit of rAL (that is, the sign bit) placed in the most significant bit of rDL. The least significant bit coming out of the shift chain is placed in the Carry flag.
Pseudocode
(rDL)[0] ← (rAL)[0]
(rDL)[1:63] ← (rAL)[0:62]
MSR[C] ← (rAL)[63]Registers Altered
- rDL
- MSR[C]
Latency
- 1 cycle