Figure 1. shi
Description
Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of register rAX and the sign-extended IMM value.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB. A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode. An unaligned data access exception occurs if the least significant bit in the address is not zero.
Pseudocode
Addr ← (rAX) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10010; ESR[S] ← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10000; ESR[S] ← 1 ; ESR[DIZ] ← No-access-allowed
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[31] ≠ 0 then
ESR[EC] ← 00001; ESR[W] ← 0; ESR[S] ← 1; ESR[Rx] ← rD
else
Mem(Addr) ← (rD)[C_DATA_SIZE-16:C_DATA_SIZE-1]Registers Altered
- MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
- ESR[EC], ESR[S], if an exception is generated
- ESR[DIZ], if a data storage exception is generated
- ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
- 1 cycle with
C_AREA_OPTIMIZED=0 or 2 - 2 cycles with
C_AREA_OPTIMIZED=1