sh - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. sh

Description

Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of registers rAX and rBX.

If the R bit is set, a halfword reversed memory location is used and the two bytes in the halfword are reversed, storing data with the opposite endianness of the endianness defined by the E bit (if virtual protected mode is enabled).

If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding them.

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.

A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.

An unaligned data access exception occurs if the least significant bit in the address is not zero.

A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled, and the instruction is not explicitly allowed.

Pseudocode

if EA = 1 then
   Addr ← (rA) & (rB)
else
   Addr ← (rAX) + (rBX)
if TLB_Miss(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10010; ESR[S] ← 1
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10000; ESR[S] ← 1 ; ESR[DIZ] ← No-access-allowed
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[31] ≠ 0 then
   ESR[EC] ← 00001; ESR[W] ← 0; ESR[S] ← 1; ESR[Rx] ← rD
else
   Mem(Addr) ← (rD)[C_DATA_SIZE-16:C_DATA_SIZE-1]

Registers Altered

  • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
  • ESR[EC], ESR[S], if an exception is generated
  • ESR[DIZ], if a data storage exception is generated
  • ESR[W], ESR[Rx], if an unaligned data access exception is generated

Latency

  • 1 cycle with C_AREA_OPTIMIZED=0 or 2
  • 2 cycles with C_AREA_OPTIMIZED=1

Notes

  • The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1).
  • The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32) and is using 32-bit mode (C_DATA_SIZE = 32).