sbi - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. sbi sbi Process.49 0 0 Process.44 1 1 Process.45 1 1 Process.46 1 1 Process.47 1 1 Process.48 0 0 Process.50 Process.9 rD, rAx, IMM rD, rAx, IMM Process.12 sbi sbi Sheet.18 Store Byte Immediate Store Byte Immediate Sheet.20 0 0 Sheet.23 6 6 Sheet.24 11 11 Sheet.25 16 16 Sheet.27 31 31 Process.59 rAx rAx Process.81 IMM IMM Process.82 rD rD

Description

Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of register rAX and the sign-extended IMM value.

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.

A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.

Pseudocode

Addr ← (rAX) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
   ESR[EC] ←   10010; ESR[S] ← 1
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10000; ESR[S] ← 1 ; ESR[DIZ] ← No-access-allowed
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else
   Mem(Addr) ← (rD)[C_DATA_SIZE-8:C_DATA_SIZE-1]

Registers Altered

  • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
  • ESR[EC], ESR[S], if an exception is generated
  • ESR[DIZ], if a data storage exception is generated

Latency

  • 1 cycle with C_AREA_OPTIMIZED=0 or 2
  • 2 cycles with C_AREA_OPTIMIZED=1

Notes

  • By default, Type B store instructions will take the 16-bit IMM field value and sign extend it to use as the immediate operand. This behavior can be overridden by preceding the instruction with an imm or imml instruction. See the instructions imm and imml for details on using immediate values.