sb - 2024.2 English

Description

Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of registers rA_X and rB_X.

If the R bit is set, a byte reversed memory location is used, storing data with the opposite endianness of the endianness defined by the E bit (if virtual protected mode is enabled).

If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding them.

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.

A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.

A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled, and the instruction is not explicitly allowed.

Pseudocode

if EA = 1 then
   Addr ← (rA) & (rB)
else
   Addr ← (rAX) + (rBX)
if TLB_Miss(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10010; ESR[S] ← 1
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10000; ESR[S] ← 1 ; ESR[DIZ] ← No-access-allowed
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else
   Mem(Addr) ← (rD)[C_DATA_SIZE-8:C_DATA_SIZE-1]

Registers Altered

• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated

Latency

• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with C_AREA_OPTIMIZED=1

Notes

• The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1).
• The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32) and is using 32-bit mode (C_DATA_SIZE = 32).