rtsd - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. rtsd rtsd Process.49 1 1 Process.44 0 0 Process.45 1 1 Process.46 1 1 Process.47 1 1 Process.48 0 0 Process.50 Process.9 rAx, IMM rAx, IMM Process.12 rtsd rtsd Sheet.18 Return from Subroutine Return from Subroutine Sheet.20 0 0 Sheet.23 6 6 Sheet.24 11 11 Sheet.25 16 16 Sheet.27 31 31 Process.59 rAx rAx Process.75 0 0 Process.76 0 0 Process.77 0 0 Process.78 1 1 Process.79 0 0 Process.80 Process.81 IMM IMM

Description

Return from subroutine will branch to the location specified by the contents of rAX plus the sign-extended IMM field.

This instruction always has a delay slot. The instruction following the RTSD is always executed before the branch target.

Pseudocode

PC ← (rAX) + sext(IMM)
allow following instruction to complete execution

Registers Altered

  • PC

Latency

  • 1 cycle (if successful branch prediction occurs)
  • 2 cycles (with Branch Target Cache disabled and C_AREA_OPTIMIZED≠2)
  • 3 cycles (if branch prediction mispredict occurs with C_AREA_OPTIMIZED=0)
  • 6 cycles (with Branch Target Cache disabled and C_AREA_OPTIMIZED=2)
  • 7 cycles (if branch prediction mispredict occurs with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

  • Convention is to use general purpose register r15 as rAX.
  • A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.