rted - 2024.2 English

Description

Return from exception will branch to the location specified by the contents of rA_X plus the sign-extended IMM field. The instruction will also enable exceptions after execution.

This instruction always has a delay slot. The instruction following the RTED is always executed before the branch target.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   PC ← (rAX) + sext(IMM)
   allow following instruction to complete execution
   MSR[EE] ← 1
   MSR[EIP] ← 0
   MSR[UM] ← MSR[UMS]
   MSR[VM] ← MSR[VMS]
   ESR ← 0

Registers Altered

• PC
• MSR[EE], MSR[EIP], MSR[UM], MSR[VM]
• ESR

Latency

• 2 cycles (with C_AREA_OPTIMIZED≠2)
• 6 cycles (with C_AREA_OPTIMIZED=2)
• If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

• Convention is to use general purpose register r17 as rA_X. This instruction requires that one or more of the MicroBlaze parameters C_*_EXCEPTION are set to 1 or that C_USE_MMU > 0.
• A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.
• The instruction should normally not be used when MSR[EE] is set, because if the instruction in the delay slot would cause an exception, the exception handler would be entered with exceptions enabled.
• Code returning from an exception must first check if MSR[DS] is set, and in that case return to the address in BTR.