rtbd - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. rtbd rtbd Process.49 1 1 Process.44 0 0 Process.45 1 1 Process.46 1 1 Process.47 1 1 Process.48 0 0 Process.50 Process.9 rAx, IMM rAx, IMM Process.12 rtbd rtbd Sheet.18 Return from Break Return from Break Sheet.20 0 0 Sheet.23 6 6 Sheet.24 11 11 Sheet.25 16 16 Sheet.27 31 31 Process.59 rAx rAx Process.75 0 0 Process.76 0 0 Process.77 1 1 Process.78 1 1 Process.79 0 0 Process.80 Process.81 IMM IMM

Description

Return from break will branch to the location specified by the contents of rAX plus the sign-extended IMM field. It will also enable breaks after execution by clearing the BIP flag in the MSR.

This instruction always has a delay slot. The instruction following the RTBD is always executed before the branch target. That delay slot instruction has breaks disabled.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   PC ← (rAX) + sext(IMM)
   allow following instruction to complete execution
   MSR[BIP] ← 0
   MSR[UM] ← MSR[UMS]
   MSR[VM] ← MSR[VMS]

Registers Altered

  • PC
  • MSR[BIP], MSR[UM], MSR[VM]
  • ESR[EC], in case a privileged instruction exception is generated

Latency

  • 2 cycles (with C_AREA_OPTIMIZED≠2)
  • 6 cycles (with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

  • Convention is to use general purpose register r16 as rAX.
  • A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.