Description
The contents of register rAL are subtracted from the contents of register rBL and the result is placed into register rDL. Bit 3 of the instruction (labeled as K in the figure) is set to one for the mnemonic rsublk. Bit 4 of the instruction (labeled as C in the figure) is set to one for the mnemonic rsublc. Both bits are set to one for the mnemonic rsublkc.
When an rsubl instruction has bit 3 set (rsublk, rsublkc), the carry flag will Keep its previous value regardless of the outcome of the execution of the instruction. If bit 3 is cleared (rsubl, rsublc), then the carry flag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to one (rsublc, rsublkc), the content of the carry flag (MSR[C]) affects the execution of the instruction. When bit 4 is cleared (rsubl, rsublk), the content of the carry flag does not affect the execution of the instruction (providing a normal subtraction).
Pseudocode
if C = 0 then
(rDL) ← (rBL) + (rAL) + 1
else
(rDL) ← (rBL) + (rAL) + MSR[C]
if K = 0 then
MSR[C] ← CarryOut64
Registers Altered
- rDL
- MSR[C]
Latency
- 1 cycle
Notes
- In subtractions, Carry = (Borrow). When the Carry is set by a subtraction, it means that there is no Borrow, and when the Carry is cleared, it means that there is a Borrow.