putd - 2025.1 English - UG984

Description

MicroBlaze will write the value from register rA to the link interface defined by the four least significant bits in rB. If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits in rB, the used link is undefined.

The putd instruction has 16 variants.

The blocking versions (when ‘n’ is ‘0’) will stall MicroBlaze until there is space available in the interface. The non-blocking versions will not stall MicroBlaze and will set carry to ‘0’ if space was available and to ‘1’ if no space was available.

Except for the test versions, all data putd instructions (when ‘c’ is ‘0’) will set the control bit to the interface to ‘0’ and all control putd instructions (when ‘c’ is ‘1’) will set the control bit to ‘1’.

The test versions (when ‘t’ bit is ‘1’) will be handled as the normal case, except that the write signal to the link is not asserted (thus no source register is required) and link data is not assigned.

Atomic versions (when ‘a’ bit is ‘1’) are not interruptible. Each atomic instruction prevents the subsequent instruction from being interrupted. This means that a sequence of atomic instructions can be grouped together without an interrupt breaking the program flow. However, exceptions might still occur.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and not explicitly allowed by setting C_MMU_PRIVILEGED_INSTR to 1 these instructions are privileged. This means that if these instructions are attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   x ← rB[28:31]
   if x >= C_FSL_LINKS then
      x ← undefined
   if (t = 0) then
      Mx_AXIS_TDATA ← (rA)
   if (n = 1) then
      MSR[Carry]  ← Mx_AXIS_TVALID ˄ Mx_AXIS_TREADY
   if (t = 0) then
      Mx_AXIS_TLAST ← C

Registers Altered

• MSR[Carry]
• ESR[EC], in case a privileged instruction exception is generated

Latency

• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with C_AREA_OPTIMIZED=1

Notes

• The blocking versions of this instruction should not be placed in a delay slot, because this prevents interrupts from being served.
• These instructions are only available when the MicroBlaze parameter C_FSL_LINKS is greater than 0 and the parameter C_USE_EXTENDED_FSL_INSTR is set to 1.

  It is not recommended to allow these instructions in user mode, unless absolutely necessary for performance reasons, because that removes all hardware protection preventing incorrect use of a link.