mts - 2024.2 English

Description

Copies the contents of register rD into the special purpose register rS. The special purpose registers TLBLO and TLBHI are used to copy to the Unified TLB entry indexed by TLBX.

If the E bit is set, the extended part of the special register is moved. The TLBLO register has an extended part when the Physical Address Extension (PAE) is enabled.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

With low-latency interrupt mode (C_USE_INTERRUPT = 2), the Interrupt_Ack output port is set to 11 if the MSR{IE] bit is set by executing this instruction.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   if E = 1 then
      if (rS) = 0x1003 then
         TLBLO[0:C_ADDR_SIZE-32-1] ← (rA)
   else
      switch (rS)
           case 0x0001 : MSR  ← (rA)
           case 0x0007 : FSR  ← (rA)
           case 0x0800 : SLR ← (rA)
           case 0x0802 : SHR ← (rA)
           case 0x1000 : PID ← (rA)
           case 0x1001 : ZPR ← (rA)
           case 0x1002 : TLBX ← (rA)
           case 0x1003 : TLBLO[C_ADDR_SIZE-32:C_ADDR_SIZE-1] ← (rA)
           case 0x1004 : TLBHI ← (rA)
           case 0x1005 : TLBSX ← (rA)
      if (rS) = 0x0001 and (rA) & 2
         Interrupt_Ack ← 11

Registers Altered

• rS
• ESR[EC], in case a privileged instruction exception is generated

Latency

• 1 cycle

Notes

• When writing MSR using MTS, all bits take effect one cycle after the instruction has been executed. An MTS instruction writing MSR should never be followed back-to-back by an instruction that uses the MSR content. When clearing the IE bit, it is guaranteed that the processor will not react to any interrupt for the subsequent instructions. When setting the EIP or BIP bit, it is guaranteed that the processor will not react to any interrupt or normal hardware break for the subsequent instructions.
• To refer to special purpose registers in assembly language, use rmsr for MSR, rfsr for FSR, rslr for SLR, rshr for SHR, rpid for PID, rzpr for ZPR, rtlblo for TLBLO, rtlbhi for TLBHI, rtlbx for TLBX, and rtlbsx for TLBSX.
• The PC, ESR, EAR, BTR, EDR, and PVR0 - PVR12 cannot be written by the MTS instruction.
• The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0.
• The SLR and SHR are only valid as a destination if the MicroBlaze parameter C_USE_STACK_PROTECTION is set to 1.
• PID, ZPR and, TLBSX are only valid as destinations when the parameter C_USE_MMU > 1 (User Mode) and the parameter C_MMU_TLB_ACCESS > 1 (Read). TLBLO, TLBHI, and TLBX are only valid as destinations when the parameter C_USE_MMU > 1 (User Mode).
• When changing MSR[VM] or PID the instruction must always be followed by a synchronizing branch instruction, for example BRI 4.
• After writing to TLBHI to invalidate one or more UTLB entries, an MBAR 1 instruction must be issued to ensure that coherency is preserved in a coherent multi-processor system.
• When PAE is enabled, the entire TLBLO register must be written, by first using the extended instruction to write the most significant bits immediately followed by the least significant bits.
• The extended instruction is only valid if MicroBlaze is configured to use the MMU in virtual mode (C_USE_MMU = 3) and extended address (C_ADDR_SIZE > 32).