mfs - 2024.2 English

Figure 1. mfs

Description

Copies the contents of the special purpose register rS into register rD. The special purpose registers TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.

If the E bit is set, the extended part of the special register is moved. The EAR, PVR[8] and PVR[9} registers have extended parts when extended addressing is enabled (C_ADDR_SIZE > 32), and the TLBLO, PVR[6] and PVR[7] registers have extended parts when Physical Address Extension (PAE) is enabled.

Pseudocode

if E = 1 then
   switch (rS):
   case 0x0003 : (rD) ← EAR [0:C_ADDR_SIZE-32-1]
   case 0x1003 : (rD) ← TLBLO[0:C_ADDR_SIZE-32-1]
   case 0x2006 : (rD) ← PVR6[0:C_ADDR_SIZE-32-1]
   case 0x2007 : (rD) ← PVR7[0:C_ADDR_SIZE-32-1]
   case 0x2008 : (rD) ← PVR8[0:C_ADDR_SIZE-32-1]
   case 0x2009 : (rD) ← PVR9[0:C_ADDR_SIZE-32-1]
   default : (rD) ← Undefined
else
   switch (rS):
   case 0x0000 : (rD) ← PC
   case 0x0001 : (rD) ← MSR
   case 0x0003 : (rD) ← EAR[C_ADDR_SIZE-32:C_ADDR_SIZE-1]
   case 0x0005 : (rD) ← ESR
   case 0x0007 : (rD) ← FSR
   case 0x000B : (rD) ← BTR
   case 0x000D : (rD) ← EDR
   case 0x0800 : (rD) ← SLR
   case 0x0802 : (rD) ← SHR
   case 0x1000 : (rD) ← PID
   case 0x1001 : (rD) ← ZPR
   case 0x1002 : (rD) ← TLBX
   case 0x1003 : (rD) ← TLBLO[C_ADDR_SIZE-32:C_ADDR_SIZE-1]
   case 0x1004 : (rD) ← TLBHI
   case 0x200x : (rD) ← PVRx[C_ADDR_SIZE-32:C_ADDR_SIZE-1] (x = 0 to 12)
   default : (rD) ← Undefined

Registers Altered

rD

Latency

1 cycle

Notes

To refer to special purpose registers in assembly language, use rpc for PC, rmsr for MSR, rear for EAR, resr for ESR, rfsr for FSR, rbtr for BTR, redr for EDR, rslr for SLR, rshr for SHR, rpid for PID, rzpr for ZPR, rtlblo for TLBLO, rtlbhi for TLBHI, rtlbx for TLBX, and rpvr0 - rpvr12 for PVR0 - PVR12.
The value read from MSR might not include effects of the immediately preceding instruction (dependent on pipeline stall behavior). An instruction that does not affect MSR must precede the MFS instruction to guarantee correct MSR value.
The value read from FSR might not include effects of the immediately preceding instruction (dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the MFS instruction to guarantee correct FSR value.
EAR, ESR, and BTR are only valid as operands when at least one of the MicroBlaze C_*_EXCEPTION parameters are set to 1.
EDR is only valid as operand when the parameter C_FSL_EXCEPTION is set to 1 and the parameter C_FSL_LINKS is greater than 0.
FSR is only valid as an operand when the C_USE_FPU parameter is greater than 0.
SLR and SHR are only valid as an operand when the C_USE_STACK_PROTECTION parameter is set to 1.
PID, ZPR, TLBLO, and TLBHI are only valid as operands when the parameter C_USE_MMU > 1 (User Mode) and the parameter C_MMU_TLB_ACCESS = 1 (Read) or 3 (Full).
TLBX is only valid as operand when the parameter C_USE_MMU > 1 (User Mode) and the parameter C_MMU_TLB_ACCESS > 0 (Minimal).
PVR0 is only valid as an operand when C_PVR is 1 (Basic) or 2 (Full), and PVR1 - PVR12 are only valid as operands when C_PVR is set to 2 (Full).
The extended instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).