lw - 2024.2 English

Description

Loads a word (32 bits) from the word aligned memory location that results from adding the contents of registers rA_X and rB_X. The data is placed in least significant word of register rD_X and the most significant word (if any) is cleared.

If the R bit is set, the bytes in the loaded word are reversed, loading data with the opposite endianness of the endianness defined by the E bit (if virtual protected mode is enabled).

If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding them.

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.

A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and virtual protected mode enabled.

An unaligned data access exception occurs if the two least significant bits in the address are not zero.

A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled, and the instruction is not explicitly allowed.

Pseudocode

if EA = 1 then
   Addr ← (rA) & (rB)
else
   Addr ← (rAX) + (rBX)
if TLB_Miss(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10010; ESR[S] ← 0
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
   ESR[EC] ← 10000; ESR[S] ← 0 ; ESR[DIZ] ← 1
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[30:31] ≠ 0 then
   ESR[EC] ← 00001; ESR[W] ← 1; ESR[S] ← 0; ESR[Rx] ← rD
else
   (rDX[C_DATA_SIZE-32:C_DATA_SIZE-1]) ← Mem(Addr)
   (rDX[0:C_DATA_SIZE-33]) ← 0

Registers Altered

• rD_X, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated

Latency

• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with C_AREA_OPTIMIZED=1

Notes

• The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1).
• The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32) and is using 32-bit mode (C_DATA_SIZE = 32).