lli - 2024.2 English

Description

Loads a long (64 bits) from the long aligned memory location that results from adding the contents of register rA_L and the sign-extended IMM value. The data is placed in register rD_L.

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.

A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and virtual protected mode enabled.

An unaligned data access exception occurs if the three least significant bits in the address are not zero

Pseudocode

Addr ← (rAL) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
   ESR[EC] ← 10010;  ESR[S] ← 0
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
   ESR[EC] ← 10000; ESR[S] ← 0 ; ESR[DIZ] ← 1
   MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[C_ADDR_SIZE-3:C_ADDR_SIZE-1] ≠ 0 then
   ESR[EC] ← 00001; ESR[W] ← 1; ESR[S] ← 0 ; ESR[Rx] ← rD
else
   (rDL) ← Mem(Addr)

Registers Altered

• rD_L, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated

Latency

• 2 cycles with C_AREA_OPTIMIZED=0 or 2
• 3 cycles with C_AREA_OPTIMIZED=1

Notes

• By default, Type B load immediate instructions will take the 16-bit IMM field value and sign extend it to 64 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm or imml instruction. See the instructions imm and imml for details on using 64-bit immediate values.