Description
Loads a long (64 bits) from the long aligned memory location that results from adding the contents of registers rAL and rBL. The data is placed in register rDL.
If the R bit is set, the bytes in the loaded word are reversed, loading data with the opposite endianness of the endianness defined by the E bit (if virtual protected mode is enabled).
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and virtual protected mode enabled.
An unaligned data access exception occurs if the three least significant bits in the address are not zero.
Pseudocode
Addr ← (rAL) + (rBL)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10010; ESR[S] ← 0
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC] ← 10000; ESR[S] ← 0 ; ESR[DIZ] ← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[C_ADDR_SIZE-3:C_ADDR_SIZE-1] ≠ 0 then
ESR[EC] ← 00001; ESR[W] ← 1; ESR[S] ← 0; ESR[Rx] ← rD
else
(rDL) ← Mem(Addr)Registers Altered
- rDL, unless an exception is generated, in which case the register is unchanged
- MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
- ESR[EC], ESR[S], if an exception is generated
- ESR[DIZ], if a data storage exception is generated
- ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
- 2 cycles with
C_AREA_OPTIMIZED=0 or 2 - 3 cycles with
C_AREA_OPTIMIZED=1
Notes
- The long reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(
C_USE_REORDER_INSTR= 1).