Figure 1. lhui
Description
Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of register rAX and the sign-extended value in IMM. The data is placed in the least significant halfword of register rDX and the other halfwords in rDX is cleared.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB. A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and virtual protected mode enabled. An unaligned data access exception occurs if the least significant bit in the address is not zero.
Pseudocode
Addr ← (rAX) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10010; ESR[S] ← 0
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC] ← 10000; ESR[S] ← 0 ; ESR[DIZ] ← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[31] ≠ 0 then
ESR[EC] ← 00001; ESR[W] ← 0; ESR[S] ← 0; ESR[Rx] ← rD
else
(rDX)[C_DATA_SIZE-16:C_DATA_SIZE-1] ← Mem(Addr)
(rDX)[0:C_DATA_SIZE-17] ← 0Registers Altered
- rDX, unless an exception is generated, in which case the register is unchanged
- MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated
- ESR[EC], ESR[S], if an exception is generated
- ESR[DIZ], if a data storage exception is generated
- ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
- 1 cycle with
C_AREA_OPTIMIZED=0 or 2 - 2 cycles with
C_AREA_OPTIMIZED=1