Figure 1. lbui
Description
Loads a byte (8 bits) from the memory location that results from adding the contents of register rAX with the sign-extended value in IMM. The data is placed in the least significant byte of register rDX and the other bytes in rDX are cleared.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and virtual protected mode enabled.
Pseudocode
Addr ← (rAx) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10010; ESR[S] ← 0
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC] ← 10000; ESR[S] ← 0 ; ESR[DIZ] ← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else
(rDx)[C_DATA_SIZE-8:C_DATA_SIZE-1] ← Mem(Addr)
(rDx)[0:C_DATA_SIZE-9] ← 0Registers Altered
- rDX, unless an exception is generated, in which case the register is unchanged
- MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
- ESR[EC], ESR[S], if an exception is generated
- ESR[DIZ], if a data storage exception is generated
Latency
- 1 cycle with
C_AREA_OPTIMIZED=0 or 2 - 2 cycles with
C_AREA_OPTIMIZED=1