get - 2024.2 English

Description

MicroBlaze will read from the link x interface and place the result in register rD. If the available number of links set by C_FSL_LINKS is less than or equal to FSLx, link 0 is used.

The get instruction has 32 variants.

The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is valid. The non-blocking versions will not stall MicroBlaze and will set carry to ‘0’ if the data was valid and to ‘1’ if the data was invalid. In case of an invalid access the destination register contents are undefined.

All data get instructions (when ‘c’ bit is ‘0’) expect the control bit from the interface to be ‘0’. If this is not the case, the instruction will set MSR[FSL] to ‘1’. All control get instructions (when ‘c’ bit is ‘1’) expect the control bit from the interface to be ‘1’. If this is not the case, the instruction will set MSR[FSL] to ‘1’.

The exception versions (when ‘e’ bit is ‘1’) will generate an exception if there is a control bit mismatch. In this case ESR is updated with EC set to the exception cause and ESS set to the link index. The target register, rD, is not updated when an exception is generated, instead the data is stored in EDR.

The test versions (when ‘t’ bit is ‘1’) will be handled as the normal case, except that the read signal to the link is not asserted.

Atomic versions (when ‘a’ bit is ‘1’) are not interruptible. Each atomic instruction prevents the subsequent instruction from being interrupted. This means that a sequence of atomic instructions can be grouped together without an interrupt breaking the program flow. However, exceptions might still occur.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and not explicitly allowed by setting C_MMU_PRIVILEGED_INSTR to 1 these instructions are privileged. This means that if these instructions are attempted in User Mode (MSR[UM]=1) a Privileged Instruction exception occurs.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   x ← FSLx
   if x >= C_FSL_LINKS then
      x ← 0
   (rD) ← Sx_AXIS_TDATA
   if (n = 1) then
      MSR[Carry] ← Sx_AXIS_TVALID
   if Sx_AXIS_TLAST ≠ c and Sx_AXIS_TVALID then
      MSR[FSL] ← 1
      if (e = 1) then
         ESR[EC] ← 00000
         ESR[ESS] ← instruction bits [28:31]
         EDR ← Sx_AXIS_TDATA

Registers Altered

• rD, unless an exception is generated, in which case the register is unchanged
• MSR[FSL]
• MSR[Carry]
• ESR[EC], in case a stream exception or a privileged instruction exception is generated
• ESR[ESS], in case a stream exception is generated
• EDR, in case a stream exception is generated

Latency

• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with C_AREA_OPTIMIZED=1

The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.

Notes

• To refer to an FSLx interface in assembly language, use rfsl0, rfsl1, ... rfsl15.
• The blocking versions of this instruction should not be placed in a delay slot when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, because this prevents interrupts from being served.
• For non-blocking versions, an rsubc instruction can be used to decrement an index variable.
• The ‘e’ bit does not have any effect unless C_FSL_EXCEPTION is set to 1.
• These instructions are only available when the MicroBlaze parameter C_FSL_LINKS is greater than 0.
• The extended instructions (exception, test, and atomic versions) are only available when the MicroBlaze parameter C_USE_EXTENDED_FSL_INSTR is set to 1.
• It is not recommended to allow these instructions in user mode, unless absolutely necessary for performance reasons, because that removes all hardware protection preventing incorrect use of a link.