Figure 1. fmul
Description
The floating-point value in rA is multiplied with the floating-point value in rB and the result is placed into register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
(rD) ← 0xFFC00000
FSR[DO] ← 1
ESR[EC] ← 00110
else
if isSigNaN(rA) or isSigNaN(rB) or (isZero(rA) and isInfinite(rB)) or
(isZero(rB) and isInfinite(rA)) then
(rD) ← 0xFFC00000
FSR[IO] ← 1
ESR[EC] ← 00110
else if isQuietNaN(rA) or isQuietNaN(rB) then
(rD) ← 0xFFC00000
else if isDnz((rB)*(rA)) then
(rD) ← signZero((rA)*(rB))
FSR[UF] ← 1
ESR[EC] ← 00110
else if isNaN((rB)*(rA)) then
(rD) ← signInfinite((rB)*(rA))
FSR[OF] ← 1
ESR[EC] ← 00110
else
(rD) ← (rB) * (rA)Registers Altered
- rD, unless an FP exception is generated, in which case the register is unchanged
- ESR[EC], if an FP exception is generated
- FSR[IO,UF,OF,DO]
Latency
- 4 cycles with
C_AREA_OPTIMIZED=0 - 6 cycles with
C_AREA_OPTIMIZED=1 - 1 cycle with
C_AREA_OPTIMIZED=2
Note
This instruction is only available when the MicroBlaze parameter
C_USE_FPU is greater than 0.