Description
The floating-point value in rB is compared with the floating-point value in rA and the comparison result is placed into register rD. The OpSel field in the instruction code determines the type of comparison performed.
Pseudocode
if isDnz(rA) or isDnz(rB) then
(rD) ← 0
FSR[DO] ← 1
ESR[EC] ← 00110
else
{read out behavior from Table 1}
Registers Altered
- rD, unless an FP exception is generated, in which case the register is unchanged
- ESR[EC], if an FP exception is generated
- FSR[IO,DO]
Latency
- 1 cycle with
C_AREA_OPTIMIZED
=0 or 2 - 3 cycles with
C_AREA_OPTIMIZED
=1
Note
These instructions are only available when the MicroBlaze
parameter C_USE_FPU
is greater than 0.
The following table lists the floating-point comparison operations.
Description | OpSel | (rB) > (rA) | (rB) < (rA) | (rB) = (rA) |
isSigNaN(rA) or isSigNaN(rB) |
isQuietNaN(rA) or isQuietNaN(rB) |
---|---|---|---|---|---|---|
Comparison Type | Operand Relationship | |||||
Unordered | 000 | (rD) ← 0 | (rD) ← 0 | (rD) ← 0 |
(rD) ← 1 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 1 |
Less-than | 001 | (rD) ← 0 | (rD) ← 1 | (rD) ← 0 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Equal | 010 | (rD) ← 0 | (rD) ← 0 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 |
Less-or-equal | 011 | (rD) ← 0 | (rD) ← 1 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Greater-than | 100 | (rD) ← 1 | (rD) ← 0 | (rD) ← 0 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Not-equal | 101 | (rD) ← 1 | (rD) ← 1 | (rD) ← 0 |
(rD) ← 1 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 1 |
Greater-or-equal | 110 | (rD) ← 1 | (rD) ← 0 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |