Figure 1. fadd
Description
The floating-point sum of registers rA and rB, is placed into register rD.
Pseudocode
if isDnz(rA) or isDnz(rB) then
(rD) ← 0xFFC00000
FSR[DO] ← 1
ESR[EC] ← 00110
else if isSigNaN(rA) or isSigNaN(rB)or
(isPosInfinite(rA) and isNegInfinite(rB)) or
(isNegInfinite(rA) and isPosInfinite(rB))) then
(rD) ← 0xFFC00000
FSR[IO] ← 1
ESR[EC] ← 00110
else if isQuietNaN(rA) or isQuietNaN(rB) then
(rD) ← 0xFFC00000
else if isDnz((rA)+(rB)) then
(rD) ← signZero((rA)+(rB))
FSR[UF] ← 1
ESR[EC] ← 00110
else if isNaN((rA)+(rB)) then
(rD) ← signInfinite((rA)+(rB))
FSR[OF] ← 1
ESR[EC] ← 00110
else
(rD) ← (rA) + (rB)Registers Altered
- rD, unless an FP exception is generated, in which case the register is unchanged
- ESR[EC], if an FP exception is generated
- FSR[IO,UF,OF,DO]
Latency
- 4 cycles with C_AREA_OPTIMIZED=0
- 6 cycles with C_AREA_OPTIMIZED=1
- 1 cycle with C_AREA_OPTIMIZED=2
Note
This instruction is only available when the MicroBlaze parameter
C_USE_FPU is greater than 0.