ddiv - 2024.2 English

Description

The double precision floating-point value in rB_L is divided by the double floating-point value in rA_L and the result is placed into register rD_L.

Pseudocode

if isDnz(rAL) or isDnz(rBL) then
   (rDL) ← 0xFFF8000000000000
   FSR[DO] ← 1
   ESR[EC] ← 00110
else
   if isSigNaN(rAL) or isSigNaN(rBL) or (isZero(rAL) and isZero(rBL)) or
         (isInfinite(rAL) and isInfinite(rBL)) then
      (rDL) ← 0xFFF8000000000000
      FSR[IO] ← 1
      ESR[EC] ← 00110
   else if isQuietNaN(rAL) or isQuietNaN(rBL) then
      (rDL) ← 0xFFF8000000000000
   else if isZero(rAL) and not isInfinite(rBL) then
      (rDL) ← signInfinite((rBL)/(rAL))
      FSR[DZ] ← 1
      ESR[EC] ← 00110
   else    if isDnz((rBL) / (rAL)) then
      (rDL) ← signZero((rBL) / (rAL))
      FSR[UF] ← 1
      ESR[EC] ← 00110
   else if isNaN((rBL)/(rAL)) then
      (rDL) ← signInfinite((rBL) / (rAL))
      FSR[OF] ← 1
      ESR[EC] ← 00110
   else
      (rDL) ← (rBL) / (rAL)

Registers Altered

• rD_L, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
• FSR[IO,UF,OF,DO,DZ]

Latency

• 28 cycles with C_AREA_OPTIMIZED=0
• 30 cycles with C_AREA_OPTIMIZED=1
• 24 cycles with C_AREA_OPTIMIZED=2

Notes

• This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.