Figure 1. dcmp
Description
The double precision floating-point value in rBL is compared with the double precision floating-point value in rAL and the comparison result is placed into register rD. The OpSel field in the instruction code determines the type of comparison performed.
Pseudocode
if isDnz(rAL) or isDnz(rBL) then
(rD) ← 0
FSR[DO] ← 1
ESR[EC] ← 00110
else
{read out behavior from Table: Table 1}
Registers Altered
- rDL, unless an FP exception is generated, in which case the register is unchanged
- ESR[EC], if an FP exception is generated
- FSR[IO,DO]
Latency
- 1 cycle with
C_AREA_OPTIMIZED
=0 or 2 - 3 cycles with
C_AREA_OPTIMIZED
=1
Notes
- These instructions are only available when the MicroBlaze parameter
C_USE_FPU
is greater than 0.
Comparison Type | Operand Relationship | |||||
---|---|---|---|---|---|---|
Description | OpSel | (rBL) > (rAL) | (rBL) < (rAL) | (rBL) = (rAL) |
isSigNaN(rAL) or isSigNaN(rBL) |
isQuietNaN(rAL) or isQuietNaN(rBL) |
Unordered | 000 | (rD) ← 0 | (rD) ← 0 | (rD) ← 0 |
(rD) ← 1 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 1 |
Less-than | 001 | (rD) ← 0 | (rD) ← 1 | (rD) ← 0 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Equal | 010 | (rD) ← 0 | (rD) ← 0 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 |
Less-or-equal | 011 | (rD) ← 0 | (rD) ← 1 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Greater-than | 100 | (rD) ← 1 | (rD) ← 0 | (rD) ← 0 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
Not-equal | 101 | (rD) ← 1 | (rD) ← 1 | (rD) ← 0 |
(rD) ← 1 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 1 |
Greater-or-equal | 110 | (rD) ← 1 | (rD) ← 0 | (rD) ← 1 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |
(rD) ← 0 FSR[IO] ← 1 ESR[EC] ← 00110 |