Figure 1. dbl
Description
Converts the signed long value in register rAL to double precision floating-point and puts the result in register rDL. This is a 64-bit rounding signed conversion that will produce a 64-bit floating-point result.
Pseudocode
(rDL) ← double ((rAL))
Registers Altered
- rDL
Latency
- 5 cycles with
C_AREA_OPTIMIZED
=0 - 7 cycles with
C_AREA_OPTIMIZED
=1 - 2 cycles with
C_AREA_OPTIMIZED
=2
Notes
- This instruction is only available when the MicroBlaze parameter
C_USE_FPU
is set to 2 (Extended).