dadd - 2024.2 English

Description

The double precision floating-point sum of registers rA_L and rB_L, is placed into register rD_L.

Pseudocode

if isDnz(rAL) or isDnz(rBL) then
   (rDL) ← 0xFFF8000000000000
   FSR[DO] ← 1
   ESR[EC] ← 00110
else if isSigNaN(rAL) or isSigNaN(rBL)or
         (isPosInfinite(rAL) and isNegInfinite(rBL)) or
         (isNegInfinite(rAL) and isPosInfinite(rBL))) then
   (rDL) ← 0xFFF8000000000000
   FSR[IO] ← 1
   ESR[EC] ← 00110
else if isQuietNaN(rAL) or isQuietNaN(rBL) then
   (rDL) ← 0xFFF8000000000000
else if isDnz((rAL)+(rBL)) then
   (rDL) ← signZero((rAL)+(rBL))
   FSR[UF] ← 1
   ESR[EC] ← 00110
else if isNaN((rAL)+(rBL)) then
   (rDL) ← signInfinite((rAL)+(rBL))
   FSR[OF] ← 1
   ESR[EC] ← 00110
else
   (rDL) ← (rAL) + (rBL)

Registers Altered

• rD_L, unless an FP exception is generated, in which case the register is unchanged
• ESR[EC], if an FP exception is generated
• FSR[IO,UF,OF,DO]

Latency

• 4 cycles with C_AREA_OPTIMIZED=0
• 6 cycles with C_AREA_OPTIMIZED=1
• 1 cycle with C_AREA_OPTIMIZED=2

Notes

• This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0.