Figure 1. cmpl
Description
The contents of register rAL are subtracted from the contents of register rBL and the result is placed into register rDL.
The MSB bit of rDL is adjusted to shown true relation between rAL and rBL. If the U bit is set, rAL and rBL is considered unsigned values. If the U bit is clear, rAL and rBL is considered signed values.
Pseudocode
(rDL) ← (rBL) + (rAL) + 1
(rDL)(MSB) ← (rAL) > (rBL)Registers Altered
- rDL
Latency
- 1 cycle