bsi - 2024.2 English

Description

The first three instructions shift the contents of register rA by the amount specified by IMM and put the result in register rD.

Barrel Shift Extract Field extracts a bit field from register rA and puts the result in register rD. The bit field width is specified by IMM_W and the shift amount is specified by IMM_S. The bit field width must be in the range 1 - 31, and the condition IMM_W + IMM_S≤32 must apply.

Barrel Shift Insert Field inserts a bit field from register rA into register rD, modifying the existing value in register rD. The bit field width is defined by IMM_W - IMM_S + 1, and the shift amount is specified by IMM_S. The condition IMM_W ≥ IMM_S must apply.

The mnemonic bslli sets the S bit (Side bit). If the S bit is set, the barrel shift is done to the left. The mnemonics bsrli and bsrai clear the S bit and the shift is done to the right.

The mnemonic bsrai sets the T bit (Type bit). If the T bit is set, the barrel shift performed is Arithmetical. The mnemonics bsrli and bslli clear the T bit and the shift performed is Logical.

The mnemonic bsefi sets the E bit (Extract bit). In this case the S and T bits are not used.

The mnemonic bsifi sets the I bit (Insert bit). In this case the S and T bits are not used.

Pseudocode

if E = 1 then
   (rD)[0:31-IMMW] ← 0
   (rD)[32-IMMW:31] ← (rA) >> IMMS
else if I = 1 then
   mask ← (0xffffffff << (IMMW + 1)) ⊕  (0xffffffff << IMMS)
   (rD) ← ((rA) << IMMS) ˄ mask) ˅ ((rD) ˄ mask)
else if S = 1 then
   (rD) ← (rA) << IMM
else if T = 1 then
   if IMM ≠ 0 then
      (rD)[0:IMM-1] ← (rA)[0]
      (rD)[IMM:31] ← (rA) >> IMM
   else
      (rD) ← (rA)
else
   (rD) ← (rA) >>   IMM

Registers Altered

• rD

Latency

• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with C_AREA_OPTIMIZED=1

Notes

• These are not Type B Instructions. There is no effect from a preceding imm instruction.
• These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions (C_USE_BARREL=1).
• The assembler code "bsifi rD, rA, width, shift" denotes the actual bit field width, not the IMM_W field, which is computed by IMM_W = shift + width - 1.