brki - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. brki brki Process.49 0 0 Process.44 0 0 Process.45 1 1 Process.46 1 1 Process.47 1 1 Process.48 1 1 Process.50 Process.9 rD, IMM rD, IMM Process.12 brki brki Process.14 rD rD Process.16 IMM IMM Sheet.18 Break Immediate Break Immediate Sheet.20 0 0 Sheet.23 6 6 Sheet.24 11 11 Sheet.25 16 16 Sheet.27 31 31 Process.52 1 1 Process.53 1 1 Process.54 0 0 Process.55 0 0 Process.56 0 0 Process.57

Description

Branch and link to the instruction located at address value in IMM, sign-extended to 32 bits. The current value of PC will be stored in rD. The BIP flag in the MSR will be set, except in case of a Software Break, and the reservation bit will be cleared.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged, except as a special case when "brki rD, C_BASE_VECTORS+0x8" or "brki rD, C_BASE_VECTORS+0x18" is used to perform a Software Break. This means that, apart from the special case, if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and "brki rD, C_BASE_VECTORS+0x8" or "brki rD, C_BASE_VECTORS+0x18" is used to perform a Software Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.

Pseudocode

if MSR[UM] and IMM ≠ C_BASE_VECTORS+0x8 and IMM ≠ C_BASE_VECTORS+0x18 then
   ESR[EC] ← 00111
else
   (rD) ← PC
   PC ← sext(IMM)
   if IMM ≠ 0x18 then
      MSR[BIP] ← 1
   Reservation ← 0
   if IMM = C_BASE_VECTORS+0x8 or IMM = C_BASE_VECTORS+0x18 then
      MSR[UMS] ← MSR[UM]   
      MSR[UM] ← 0
      MSR[VMS] ← MSR[VM]
      MSR[VM] ← 0

Registers Altered

  • rD, unless an exception is generated, in which case the register is unchanged
  • PC
  • MSR[BIP], MSR[UM], MSR[VM]
  • ESR[EC], in case a privileged instruction exception is generated

Latency

  • 3 cycles (with C_AREA_OPTIMIZED≠2)
  • 7 cycles (with C_AREA_OPTIMIZED = 2)

Notes

  • By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction imm for details on using immediate values.
  • As a special case, the imm instruction does not override a Software Break “brki rD, 0x18” when C_DEBUG_ENABLED. is greater than zero, irrespective of the value of C_BASE_VECTORS, to allow Software Break after an imm instruction.
  • With 64-bit mode, the instruction can also be preceded by an imml instruction, uses the entire 64-bit register rDL, and can be used for extended address branches.