brk - 2024.2 English

Description

Branch and link to the instruction located at address value in rB. The current value of PC will be stored in rD. The BIP flag in the MSR will be set, and the reservation bit will be cleared.

When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.

Pseudocode

if MSR[UM] = 1 then
   ESR[EC] ← 00111
else
   (rD) ← PC
   PC ← (rB)
   MSR[BIP] ← 1
   Reservation ← 0

Registers Altered

• rD
• PC
• MSR[BIP]
• ESR[EC], in case a privileged instruction exception is generated

Latency

• 3 cycles (with C_AREA_OPTIMIZED≠2)
• 7 cycles (with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Note

With 64-bit mode, the instruction uses the entire 64-bit registers rB_L and rD_L, and can be used for extended address branches.