bri - 2024.2 English

Description

Branch to the instruction located at address determined by IMM, sign-extended to 32 bits.

The mnemonics brlid and bralid will set the L bit. If the L bit is set, linking will be performed. The current value of PC will be stored in rD.

The mnemonics brai, braid, and bralid will set the A bit. If the A bit is set, it means that the branch is to an absolute value and the target is the value in IMM, otherwise, it is a relative branch and the target will be PC + IMM.

The mnemonics brid, braid, brlid, and bralid will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and "bralid rD, C_BASE_VECTORS+0x8" is used to perform a User Vector Exception, the Machine Status Register bits User Mode and Virtual Mode are cleared.

Pseudocode

if L = 1 then
   (rD) ← PC
if A = 1 then
   PC ← sext(IMM)
else
   PC ← PC + sext(IMM)
if D = 1 then
   allow following instruction to complete execution
if D = 1 and A = 1 and L = 1 and IMM = C_BASE_VECTORS+0x8 then
      MSR[UMS] ← MSR[UM]
      MSR[VMS] ← MSR[VM]
      MSR[UM]  ← 0
      MSR[VM]  ← 0

Registers Altered

• rD
• PC
• MSR[UM], MSR[VM]

Latency

• 1 cycle (if successful branch prediction occurs)
• 2 cycles (if the D bit is set with C_AREA_OPTIMIZED≠2)
• 3 cycles (if the D bit is not set with C_AREA_OPTIMIZED≠2, or a branch prediction mispredict occurs with C_AREA_OPTIMIZED=0)
• 6 cycles (if the D bit is set with C_AREA_OPTIMIZED=2)
• 7 cycles (if the D bit is not set, or if branch prediction mispredict occurs with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

• The instructions brli and brali are not available.
• By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction imm for details on using immediate values.
• A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.
• With 64-bit mode, the absolute branch instructions brai, braid, and bralid can also be preceded by an imml instruction, bralid uses the entire 64-bit registers rD_L, and the instructions can be used for extended address branches.