breai - 2024.2 English

Description

Branch to the instruction located at address determined by PC + IMM, extended with the immediate value from the preceding IMM or imml instructions.

The mnemonic brealid will set the L bit. If the L bit is set, linking will be performed. The current value of PC will be stored in rD_L.

The mnemonics breaid and brealid will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

Pseudocode

if L = 1 then
   (rDL) ← PC
PC ← PC + sext(IMM)
if D = 1 then
   allow following instruction to complete execution

Registers Altered

• rD_L
• PC

Latency

• 1 cycle (if successful branch prediction occurs)
• 2 cycles (if the D bit is set with C_AREA_OPTIMIZED≠2)
• 3 cycles (if the D bit is not set with C_AREA_OPTIMIZED≠2, or a branch prediction mispredict occurs with C_AREA_OPTIMIZED=0)
• 6 cycles (if the D bit is set with C_AREA_OPTIMIZED=2)
• 7 cycles (if the D bit is not set, or if branch prediction mispredict occurs with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

• The instruction breali is not available.
• Absolute extended address branches can be performed with the instructions brai, braid, and bralid.
• By default, Type B Branch Long Instructions will take the 16-bit IMM field value and sign extend it to 64 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm or imml instruction. See the instructions imm and imml for details on using 64-bit immediate values.
• A delay slot must not be used by the following: imm, imml, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.