Description
Branch to the instruction located at address determined by rB.
The mnemonics brld and brald will set the L bit. If the L bit is set, linking will be performed. The current value of PC will be stored in rD.
The mnemonics bra, brad, and brald will set the A bit. If the A bit is set, it means that the branch is to an absolute value and the target is the value in rB, otherwise, it is a relative branch and the target will be PC + rB.
The mnemonics brd, brad, brld, and brald will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction.
If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.
Pseudocode
if L = 1 then
(rD) ← PC
if A = 1 then
PC ← (rB)
else
PC ← PC + (rB)
if D = 1 then
allow following instruction to complete executionRegisters Altered
- rD
- PC
Latency
- 2 cycles (if the D bit is set with
C_AREA_OPTIMIZED≠2) - 3 cycles (if the D bit is not set with
C_AREA_OPTIMIZED≠2) - 6 cycles (if the D bit is set with
C_AREA_OPTIMIZED=2) - 7 cycles (if the D bit is not set with
C_AREA_OPTIMIZED=2)
If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.
Notes
The instructions brl and bral are not available. A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.
With 64-bit mode, the absolute branch instructions bra, brad, and brald use the entire 64-bit register rBL, brald uses the entire 64-bit register rDL, and the instructions can be used for extended address branches.