bgei - 2024.2 English

Description

Branch if rA is greater or equal to 0, to the instruction located in the offset value of IMM. The target of the branch will be the instruction at address PC + IMM.

The mnemonic bgeid will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

Pseudocode

If rA >= 0 then
   PC ← PC + sext(IMM)
else
   PC ← PC + 4
if D = 1 then
   allow following instruction to complete execution

Registers Altered

• PC

Latency

• 1 cycle (if branch is not taken, or successful branch prediction occurs)
• 2 cycles (if branch is taken and the D bit is set with C_AREA_OPTIMIZED≠2)
• 3 cycles (if branch is taken and the D bit is not set with C_AREA_OPTIMIZED≠2, or a branch prediction mispredict occurs with C_AREA_OPTIMIZED=0)
• 6 cycles (if branch is taken and the D bit is set with C_AREA_OPTIMIZED=2)
• 7 cycles (if branch is taken and the D bit is not set, or if branch prediction mispredict occurs with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Notes

• By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction imm for details on using 32-bit immediate values.
• A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.