Description
Branch if rA or rAL is not equal to 0, to the instruction located in the offset value of IMM extended with the immediate value from the preceding imm or imml instructions. The target of the branch will be the instruction at address PC + IMM.
When preceded by an imml instruction, a long comparison using rAL is performed, otherwise a 32-bit comparison using rA is performed.
The mnemonic beaneid will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.
Pseudocode
If (preceded by imml) and rAL ≠ 0 then
PC ← PC + sext(IMM)
else if rA ≠ 0 then
PC ← PC + sext(IMM)
else
PC ← PC + 4
if D = 1 then
allow following instruction to complete executionRegisters Altered
- PC
Latency
- 1 cycle (if branch is not taken, or successful branch prediction occurs)
- 2 cycles (if branch is taken and the D bit is set with
C_AREA_OPTIMIZED≠2) - 3 cycles (if branch is taken and the D bit is not set with
C_AREA_OPTIMIZED≠2, or a branch prediction mispredict occurs withC_AREA_OPTIMIZED=0) - 6 cycles (if branch is taken and the D bit is set with
C_AREA_OPTIMIZED=2) - 7 cycles (if branch is taken and the D bit is not set, or if
branch prediction mispredict occurs with
C_AREA_OPTIMIZED=2)
If C_USE_MMU > 1 two additional cycles are added with
C_AREA_OPTIMIZED=2.
Notes
-
By default, Type B Branch Long Instructions will take the 16-bit IMM field value and sign extend it to 64 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm or imml instruction. See the instructions imm and imml for details on using 64-bit immediate values.
The assembler pseudo-instructions bealnei and bealneid are used to indicate a long comparison.
A delay slot must not be used by the following: imm, imml, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.