beale - 2024.2 English

Description

Branch if rA or rA_L is less or equal to 0, to the instruction located in the offset value of rB_L. The target of the branch will be the instruction at address PC + rB_L.

The mnemonics bealle and bealled will set the L bit. If the L bit is set, a long comparison using rA_L is performed, otherwise a 32-bit comparison using rA is performed.

The mnemonics bealed and bealled will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that is, in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

Pseudocode

if L = 1 and rAL <= 0 then
   PC ← PC + rBL
else if rA <= 0 then
   PC ← PC + rBL
else
   PC ← PC + 4
if D = 1 then
   allow following instruction to complete execution

Registers Altered

• PC

Latency

• 1 cycle (if branch is not taken)
• 2 cycles (if branch is taken and the D bit is set with C_AREA_OPTIMIZED≠2)
• 3 cycles (if branch is taken and the D bit is not set with C_AREA_OPTIMIZED≠2)
• 6 cycles (if branch is taken and the D bit is set with C_AREA_OPTIMIZED=2)
• 7 cycles (if branch is taken and the D bit is not set with C_AREA_OPTIMIZED=2)

If C_USE_MMU > 1 two additional cycles are added with C_AREA_OPTIMIZED=2.

Note

• A delay slot must not be used by the following: imm, imml, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.