Figure 1. andli
Description
The contents of register rAL or rDL are ANDed with the value of the IMM field extended with the immediate value from the preceding imml instructions; the result is placed into register rDL.
Pseudocode
(rDL) ← (rAL|rDL) ˄ sext(IMM)Registers Altered
- rDL
Latency
- 1 cycle
Note
- Type B logical long instructions with three operands must be preceded by an imml instruction. See the instruction imml for details on using long immediate values.