andi - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Figure 1. andi andi Process.49 1 1 Process.44 0 0 Process.45 1 1 Process.46 0 0 Process.47 1 1 Process.48 0 0 Process.50 Process.9 rD, rA, IMM rD, rA, IMM Process.12 andi andi Process.13 rA rA Process.14 rD rD Process.16 IMM IMM Sheet.18 Logical AND with Immediate Logical AND with Immediate Sheet.20 0 0 Sheet.23 6 6 Sheet.24 11 11 Sheet.25 16 16 Sheet.27 31 31

Description

The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the result is placed into register rD.

Pseudocode

(rD) ← (rA) ˄ sext(IMM)

Registers Altered

  • rD

Latency

1 cycle

Note

By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction imm for details on using 32-bit immediate values.