addli - 2024.2 English

Description

The sum of the contents of registers rA_L or rD_L and the value in the IMM field extended with the immediate value from the preceding imml instructions, if any, is placed into register rD_L. Bit 3 or 13 of the instruction (labeled as K in the figure) is set to one for the mnemonic addik. Bit 4 or 14 of the instruction (labeled as C in the figure) is set to one for the mnemonic addlic. Both bits are set to one for the mnemonic addlikc.

When an addli instruction has bit 3 or 13 set (addlik, addlikc), the carry flag will keep its previous value regardless of the outcome of the execution of the instruction. If bit 3 or 13 is cleared (addli, addlic), then the carry flag will be affected by the execution of the instruction.

When bit 4 or 14 of the instruction is set to one (addlic, addlikc), the content of the carry flag (MSR[C]) affects the execution of the instruction. When bit 4 or 14 is cleared (addli, addlik), the content of the carry flag does not affect the execution of the instruction (providing a normal addition).

Pseudocode

if C = 0 then
   (rDL) ← (rAL|rDL) + sext(IMM)
else
   (rDL) ← (rAL|rDL) + sext(IMM) + MSR[C]
if K = 0 then
   MSR[C] ← CarryOut64

Registers Altered

• rD_L
• MSR[C]

Latency

• 1 cycle

Notes

• The C bit in the instruction opcode is not the same as the carry bit in the MSR.
• Type B arithmetic long instructions with three operands must be preceded by an imml instruction. See the instruction imml for details on using long immediate values.