addl - 2024.2 English

Description

The sum of the contents of registers rA_L and rB_L, is placed into register rD_L.

Bit 3 of the instruction (labeled as K in the figure) is set to one for the mnemonic addlk. Bit 4 of the instruction (labeled as C in the figure) is set to one for the mnemonic addlc. Both bits are set to one for the mnemonic addlkc.

When an add instruction has bit 3 set (addlk, addlkc), the carry flag will Keep its previous value regardless of the outcome of the execution of the instruction. If bit 3 is cleared (addl, addlc), then the carry flag will be affected by the execution of the instruction.

When bit 4 of the instruction is set to one (addlc, addlkc), the content of the carry flag (MSR[C]) affects the execution of the instruction. When bit 4 is cleared (addl, addlk), the content of the carry flag does not affect the execution of the instruction (providing a normal addition).

Pseudocode

if C = 0 then
   (rDL) ← (rAL) + (rBL)
else
   (rDL) ← (rAL) + (rBL) + MSR[C]
if K = 0 then
   MSR[C] ← CarryOut64

Registers Altered

• rD_L
• MSR[C]

Latency

• 1 cycle

Notes

• The C bit in the instruction opcode is not the same as the carry bit in the MSR.